The I2C protocol was built to replace the difficulties of separate data bus and address bus lines with a simple 2 wire bus connection that is able to handle the communication between modules or devices within microcontroller projects.
Info is sent out serially using one line for data (typically referred to as SDA) and one for clock (known as SCL). The two wires are in an open collector/drain configuration and pulled high employing a resistor, which forms a "wired AND" circuit. A 7-bit addressing scheme is utilized, which can provide the capability to address 112 devices (16 addresses are reserved). The rate of the clock line is mostly restrained by the bus capacitance, which is four hundred pf. The transmission rate is usually 400 kHz, though there are some implementations that run faster.
Although most systems are designed such that one device is the host or "master", and the other ones are set up as peripherals, or "slaves", any device on the bus line can become a "master" and take over the bus lines for data transfer. If one device wishes data transferred from or to another IC it must wait until it sees no activity on the bus (that is,SDA and SDL are high). It will then issue a start signal, which causes all other devices to enter a "listen" mode. The new "master" will then transmit the 7-bit binary address of the correct receiver together with a read/write bit, which indicates whether the transfer will be a read or write operation.
Bytes are always transmitted MSB first. The receiver with the correct address will respond with an acknowledgement pulse. The data byte (or bytes) are then broadcast according to the read / write standing. After each data byte is sent, a confirmation pulse is sent from the receiving end to the broadcasting end. When the transfer has been finished, the master issues a stop signal. This pulls the clock line high followed by the data line, which frees the bus for another transfer.
The master always has complete control of the clock (SCL line) in a data transfer, if it is receiving or transmitting data. The "slave" can slow down the clock by holding it low temporarily if it's a slow module. The master can end the data transfer at any time by providing a stop signal, even in the middle of a byte transfer.
Info is sent out serially using one line for data (typically referred to as SDA) and one for clock (known as SCL). The two wires are in an open collector/drain configuration and pulled high employing a resistor, which forms a "wired AND" circuit. A 7-bit addressing scheme is utilized, which can provide the capability to address 112 devices (16 addresses are reserved). The rate of the clock line is mostly restrained by the bus capacitance, which is four hundred pf. The transmission rate is usually 400 kHz, though there are some implementations that run faster.
Although most systems are designed such that one device is the host or "master", and the other ones are set up as peripherals, or "slaves", any device on the bus line can become a "master" and take over the bus lines for data transfer. If one device wishes data transferred from or to another IC it must wait until it sees no activity on the bus (that is,SDA and SDL are high). It will then issue a start signal, which causes all other devices to enter a "listen" mode. The new "master" will then transmit the 7-bit binary address of the correct receiver together with a read/write bit, which indicates whether the transfer will be a read or write operation.
Bytes are always transmitted MSB first. The receiver with the correct address will respond with an acknowledgement pulse. The data byte (or bytes) are then broadcast according to the read / write standing. After each data byte is sent, a confirmation pulse is sent from the receiving end to the broadcasting end. When the transfer has been finished, the master issues a stop signal. This pulls the clock line high followed by the data line, which frees the bus for another transfer.
The master always has complete control of the clock (SCL line) in a data transfer, if it is receiving or transmitting data. The "slave" can slow down the clock by holding it low temporarily if it's a slow module. The master can end the data transfer at any time by providing a stop signal, even in the middle of a byte transfer.
About the Author:
Embedded Adventures is a website that explores embedded electronics, including devices that will communicate using I2C like a real time clock module or an air pressure sensor.
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